An integrated circuit chip (hereafter referred to as an “IC” or a “chip”) comprises cells and connections between cells formed on a surface of a semiconductor substrate. The IC may include a large number of cells and require complex connections between the cells.
A cell is a group of one or more circuit components such as transistors, capacitors, and other basic circuit elements grouped to perform a function. Each of the cells of an IC may have one or more pins, each of which, in turn, may be connected to one or more other pins of the IC by wires. The wires connecting the pins of the IC are also formed on the surface of the chip.
A net is a set of two or more pins that must be connected. Because a typical chip has numerous pins, often hundreds of thousands or more that must be connected in various combinations, there may be hundreds of thousands of nets defining the chip. Most nets define only two pins to be connected, but some nets require three or more pins, some require hundreds of pins.
A netlist is a list of nets for a chip. The netlist is useful during the design phase of the chip to identify probable performance of the chip, including its parameters such as capacitance, timing and component size.
Due to the large number of components and the details required during the fabrication process, the design of an IC is not practical without the aid of computers. As a result, most phases of chip design extensively use Computer Aided Design (CAD) tools, and many phases have already been partially or fully automated. Automation of the physical design process has increased the level of integration, reduced turn around time and enhanced chip performance.
Routing is performed to complete interconnections between groups of cells of the chip according to the specified netlist. Routing is usually done in two phases referred to as the global routing and detailed routing phases. In global routing, connections are completed between blocks of the circuit disregarding the exact geometric details of each wire and terminal. For each wire, a global router finds a list of channels that are to be used as a passageway for that wire.
Global routing is followed by detailed routing, which completes point-to-point connections between terminals on the blocks, specifying geometric information of the wires such as wire width and layer assignments.
In order for circuit designers to calculate the performance of the IC under design, the designers need to compute the delays of the cells in the IC. These delays may be in the form of propagation delay, which is the time duration a signal takes to travel from the input to the output of a cell, and the ramptime, which is the time duration that a data signal is required to be stable following its input to a cell.
To assure that signals arrive at the correct time, designers often design buffers, such as inverters, into the wire paths to perform signal delays. While placement of buffers is desirable during the global routing phase, the task is made difficult due to the varying sizes, capacitances and ramptimes of buffers. The present invention is directed to placement of buffers, including inverters, in channels during the routing stage of design for optimal performance in the IC.